ECB-BF532/schematic/SDRAM

Descripción

Esquemático que muestra las conexiones realizadas entre la SRDRAM y el BF532.

Esquemático que muestra las conexiones realizadas entre la SRDRAM y el BF532.

Diagrama de Bloques para la memoria SDRAM

The HYB39S256160FE-F are four bank Synchronous DRAMs organized as 4 banks x 4 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with Qimonda’s advanced 0.11-μm 256-MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply. The 256-Mbit component are available in P(G)–TSOPII–54 packages,

Diagrama de Bloques

La SDRAM como se puede observar cuenta con 4 bancos los cuales tienen 4 Mbit(4194304 o 3FFFFFh) de direcciones con 16 bits cada uno.

Signals Description

El control de la SDRAM se hace por medio de las siguientes señales:

SIGNAL	TYPE	Description
CLK	Input	Clock: CLK is driven by the system clock. All others signals are sampled on the rising edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE	Input	Clock Enable: CKE activates (HIGH) or deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.
CS#	Input	Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.
CAS#, RAS#, WE#	Input	Column Address Strobe - Row Address Strobe - Write Enable: defines the command being entered. Along with CS#.
DQML, DQMH	Input	Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle.
BA0, BA1	Input	Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied.
A0-A12	Input	Address Inputs: A0-A12 are sampled during the ACTIVE command (rowaddress A0-A12) and READ/WRITE command (column-address A0-A9, A11 [x4]; A0-A9 [x8]; A0-A8 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the op-code during a LOAD MODE REGISTER command.
DQ0-DQ15	Input	Data Inputs:Data Bus.

SDRAM commands

El funcionamiento de la SDRAM es controlado a través de los siguientes comandos:

Operation	Device State	CKE n-1	CKE n	DQM	BA0 BA1	AP=A10	Addr	~CS	~RAS	~CAS	~WE
Bank Active	Idle	H	X	X	V	V	V	L	L	H	H
Bank Precharge	Any	H	X	X	V	L	X	L	L	H	L
Precharge All	Any	H	X	X	X	H	X	L	L	H	L
Write	Active	H	X	X	V	L	V	L	H	L	L
Write with Auto precharge	Active	H	X	X	V	H	V	L	H	L	L
Read	Active	H	X	X	V	L	V	L	H	L	H
Read with Auto precharge	Active	H	X	X	V	H	V	L	H	L	H
Mode Register Set	Idle	H	X	X	V	V	V	L	L	L	L
No Operation	Any	H	X	X	X	X	X	L	H	H	H
Burst Stop	Active	H	X	X	X	X	X	L	H	H	L
Device Deselect	Any	H	X	X	X	X	X	H	X	X	X
Auto Refresh	Idle	H	H	X	X	X	X	L	L	L	H
Self Refresh Entry	Idle	H	L	X	X	X	X	L	L	L	H
Self Refresh Exit	Idle (Self Refr.)	L	H	X	X	X	X	H/L	X/H	X/H	X/X
Power Down/Clock Suspend Entry	Active or Idle or Burst	H	L	X	X	X	X	H/L	X/H	X/H	X/H
Power Down/ Clock Suspend Exit	Active or Idle or Burst	L	H	X	X	X	X	H/L	X/H	X/H	X/H
Data Write/ Output Enable	Active	H	X	L	X	X	X	X	X	X	X
Data Write/ Output Disable	Active	H	X	H	X	X	X	X	X	X	X

V = Valid, x = Don’t Care, L = Low Level, H = High Level

CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided.

This is the state of the banks designated by BA0, BA1 signals.

Tiempos óptimos de trabajo

Para poder trabajar de manera optima con la SDRAM se deben cumplir los siguientes requerimientos en tiepo al momento de ejecutar un comando:

Parametro	Simbolo	Min	Max	Unidad	NOTA
Reloj y habilitación de Reloj
Frecuencia de reloj	tCK	7/7.5	--/--	ns	CL3/CL2
Access Time from Clock	tAC	--/--	5.4/5.4	ns	CL3/CL2 3)4)5)
Clock High Pulse Width	tCH	2.5	—	ns
Clock Low Pulse Width	tCL	2.5	—	ns
Transition time	tT	0.3	1.2	ns
Setup and Hold Times
Input Setup Time	tIS	1.5	—	ns	6)
Input Hold Time	tIH	0.8	—	ns	6)
CKE Setup Time	tCKS	1.5	—	ns	6)
CKE Hold Time	tCKH	0.8	—	ns	6)
Mode Register Set-up to Active delay	tRSC	2	—	tCK
Power Down Mode Entry Time	tSB	0	7	ns
Common Parameters
Row to Column Delay Time	tRCD	15	—	ns	7)
Row Precharge Time	tRP	15	—	ns	7)
Row Active Time	tRAS	37	100k	ns	7)
Row Cycle Time	tRC	60	—	ns	7)
Row Cycle Time during Auto Refresh	tRFC	63	—	ns
Activate(a) to Activate(b) Command period	tRRD	14	—	ns	7)
CAS(a) to CAS(b) Command period	tCCD	1	—	tCK
Refresh Cycle
Refresh Period (8192 cycles)	tREF	–	64	ms
Self Refresh Exit Time	tSREX	1	—	tCK
Data Out Hold Time	tOH	3	—	ns	3)5)
Read Cycle
Data Out to Low Impedance Time	tLZ	0	—	ns
Data Out to High Impedance Time	tHZ	3	7	ns
DQM Data Out Disable Latency	tDQZ	—	2	tCK
Write Cycle
Last Data Input to Precharge (Write without Auto Precharge)	tWR	14	—	ns	8)
Last Data Input to Activate(Write with Auto Precharge)	tDAL(min.)	—	—	tCK	9)
DQM Write Mask Latency	tDQW	0	—	tCK

_{1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns}

_{2) For proper power-up see the operation section of this data sheet.}

_{3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.}

_{4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.}

_{5) Access time from clock tAC is 4.6 ns for PC133 components with no termination and 0 pF load,Data out hold time tOH is 1.8 ns for PC133 components with no termination and 0 pF load.}

_{6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter.}

_{7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:the number of clock cycles = specified value of timing period (counted in fractions as a whole number).}

_{8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto- Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tck greater or equal the specified tWR value, where tCK is equal to the actual system clock time.}

_{9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time.}

Tiempos para t_AC y t_OH

A continuación se visualizan los tiempos que intervienen con la adquisición y salida de datos:

SDRAM en U-boot

En el archivo: include/configs/cm-bf533.h , se configuran distintos parámetros de la memoria, frecuencia, bus externo (EBIU), tamaño, etc. Observando en detalle la sección de configuración:

1. /*

2.  * Memory Settings

3.  */

4. #define CONFIG_MEM_ADD_WDTH	9

5. /*Tamaño del Bus de Direcciones de la memoria*/       

7. #define CONFIG_MEM_SIZE		32  

8. /*32MB de Memoria disponibles */

10. #define CONFIG_EBIU_SDRRC_VAL	((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2)) 

11. /*Valor del Registro de Control de Refresco de la memoria SDRAM*/

13. #define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)  

14. /*Registro de control global para SDRAM

15. SCTLE: Activar clok de sdram

16. TRP, TRAS, TRCD, TWR, : Opciones para el ciclo de tiempo

17. */

19. #define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL) 

20. /*Registro de control general de la memoria asíncrona */

22. #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)

23. /*Registro de control Banco 0 de la memoria asíncrona */

25. #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)

26. /*Registro de control Banco 1 de la memoria asíncrona */

28. #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)

29. /*Tamaño de espacio en memoria reservado para monitorear en tiempo de compilación si el entorno está embebido en la imagen de u-boot ó 

30. localizado en otro sector flash */

32. #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)

33. /*Tamaño de espacio en memoria sdram reservado para el uso de la función malloc()*/

Nota: Los valores de los registros: EBIU_SDGCTL - EBIU_SDBCTL - EBIU_SDRRC se pueden calcular a partir de la siguiente hoja de cálculo Calcular parámetros SDRAM

Fuentes

• Datasheet HYB39S256160FE-7.
• SDRAM en la Wikipedia
• SDRAM en docs.blackfin.uclinux.org/
• Configuración básica sdram para u-boot